In the packaging of integrated circuits, device dies, which may be stacked vertically as well as horizontally, are packaged onto redistribution structures. The device dies may be bonded onto one side of a redistribution structure using flip chip bonding, and a reflow is performed to melt the solder balls that interconnect the dies and the redistribution structure. Then, a molding compound is applied on the package, with the molding compound covering the device die and the solder balls.
However, there is significant mismatch between the Coefficients of Thermal Expansion (CTEs) of the materials in the packages. For example, the redistribution structures and the molding compound have CTEs that are much higher than that of the device dies. Accordingly, in the resulting package, there is a significant warpage. The warpage in the package substrates may cause irregular joints and/or bump cracks. The warpage may be further worsened by the asymmetrical arrangement of device dies over the redistribution structures. As a result, the yield of the packaging process is adversely affected.